The present invention relates generally to data processing systems and more particularly to a priority determining system for a common bus.
A central processor is typically coupled by a common bus to a plurality of peripheral devices each of which requires access to the central processor on some priority basis. Priority determination is required for the case where two or more peripheral devices attempt to obtain control of the common bus at once. A number of prior art priority determination systems exist. One such system is described in an article entitled, "Unified Bus Maximizes Minicomputer Flexibility," by D. Chertkow et al., ELECTRONICS, Dec 21, 1970, pages 47-52. Generally the major advantage of a common or unified electrical bus is in the ability to utilize more advanced memories and peripheral equipment as the hardware becomes available. This is possible because all the devices used with a common bus send and receive address, data, and control information, by the same set of signals.
In U.S. Pat. No. 3,766,530, entitled "Communications Between Central Unit And Peripheral Units," by R. Atsushi Ito, there is disclosed a priority determining system wherein an interrogation signal is initially sent to all the peripheral devices. In response to the interrogation signal, those peripheral devices requesting service are placed in a waiting queue and are then serviced in sequence. After the servicing is completed for all devices in the queue, the following interrogation signal causes another waiting queue to be established.
It would be highly advantageous to have a priority determining system that allows the highest priority devices to have access to the common bus without the time delay encountered by having to first allow access to all the peripheral devices that make up one queue.
The present invention utilizes the advantages of the common bus without the need for establishing a waiting queue.
In U.S. Pat. No. 3,629,854, entitled, "Modular Multiprocessor System with Recirculating Priority," by E. A. Hauch et al., there is disclosed another type of priority system which operates with a common bus. The system operates by allowing each processor to scan all peripheral devices when the processor receives a priority bit. The priority bit is circulated in a closed loop, which links each of the processors. Only the processor having possession of the circulating bit is allowed access to the common bus.